Current Issue : January - March Volume : 2017 Issue Number : 1 Articles : 5 Articles
A low complexity all-digital background calibration technique based on statistics is proposed. The basic idea of the statistics\ncalibration technique is that the output average energy of each channel of TIADC will be consistent ideally, since each channel\nsamples the same input signal, and therefore the energy deviation directly reflects the mismatch errors of channels. In this work,\nthe offset mismatch and gain mismatch are calibrated by an adaptive statistics calibration algorithm based on LMS iteration; the\ntiming mis match is estimated by performing the correlation calculation of the outputs of subchannels and corrected by an improved\nfractional delay filter based on Farrow structure. Applied to a four-channel 12-bit 400MHz TIADC, simulation results show that,\nwith calibration, the SNDR raises from 22.5 dB to 71.8 dB and ENOB rises from 3.4 bits to 11.6 bits for a 164.6MHz sinusoidal input.\nCompared with traditional methods, the proposed schemes are more feasible to implement and consume less hardware resources....
In medical sciences and particular in cardiology related area, ECG machine is considered a basic equipment to get the\nfundamental knowledge about proper functioning of heart. In this work the aim is to make energy efficient ECG machine\ndesign on FPGA using capacitance scaling technique while the device is operating under various WLAN specific frequencies.\nConcept of internet of things is used in this work by adding additional 128-bit IPv6 address in the input of ECG machine\nthat will use to control the device via internet. Kintex-7 is used from the FPGA family for this task. It is analyzed that\n89.15%, 89.75% and 89.81% power reduction can be achieved under device operating frequencies 0.9 GHz, 2.4 GHz and\n3.6 GHz respectively when the capacitance is taken 500 pF in place of 5000 pF....
A novel configurable DC/DC converter architecture, to be integrated as hard macrocell in automotive embedded\nsystems, is proposed in the paper. It aims at realizing an intelligent voltage regulator. With respect to the state of\nthe art, the challenge is the integration into an automotive-qualified chip of several advanced features like dithering\nof switching frequency, nested control loops with both current and voltage feedback, asynchronous hysteretic\ncontrol for low power mode, slope control of the power FET gate driver, and diagnostic block against out-of-range\ncurrent or voltage or temperature conditions. Moreover, the converter macrocell can be connected to the invehicle\ndigital network, exchanging with the main vehicle control unit status/diagnostic flags and commands. The\nproposed design can be configured to work both in step-up and step-down modes, to face a very wide operating\ninput voltage range from 2.5 to 60 V and absolute range from âË?â??0.3 to 70 V. The main target is regulating all\nvoltages required in the emerging hybrid/electric vehicles where, besides the conventional 12 V DC bus, also a 48 V\nDC bus is present. The proposed design supports also digital configurability of the output regulated voltage,\nthrough a programmable divider, and of the coefficients of the proportional-integrative controller inside the nested\ncontrol loops. Fabricated in 0.35 Ã?¼m CMOS technology, experimental measurements prove that the IC can operate\nin harsh automotive environments since it meets stringent requirements in terms of electrostatic discharge (ESD)\nprotection, operating temperature range, out-of-range current, or voltage conditions....
Innovative systems exploring the flexibility and the transparency of modern\nsemiconducting materials are being widely researched by the scientific community and by several\ncompanies. For a low-cost production and large surface area applications, thin-film transistors (TFTs)\nare the key elements driving the system currents. In order to maintain a cost efficient integration\nprocess, solution based materials are used as they show an outstanding tradeoff between cost and\nsystem complexity. In this paper, we discuss the integration process of ZnO nanoparticle TFTs using\na high-k resin as gate dielectric. The performance in dependence on the transistor structure has\nbeen investigated, and inverted staggered setups depict an improved performance over the coplanar\ndevice increasing both the field-effect mobility and the ION/IOFF ratio. Aiming at the evaluation of\nthe TFT characteristics for digital circuit applications, inverter circuits using a load TFT in the pull-up\nnetwork and an active TFT in the pull-down network were integrated. The inverters show reasonable\nswitching characteristics and V/V gains. Conjointly, the influence of the geometry ratio and the\nsupply voltage on the devices have been analyzed. Moreover, as all integration steps are suitable to\npolymeric templates, the fabrication process is fully compatible to flexible substrates....
Based on conventional approaches for the integration of resistive-type superconducting\nfault current limiters (SFCLs) on electric distribution networks, SFCL models\nlargely rely on the insertion of a step or exponential resistance that is determined by a\npredefined quenching time. In this paper, we expand the scope of the aforementioned\nmodels by considering the actual behaviour of an SFCL in terms of the temperature\ndynamic power-law dependence between the electrical field and the current density,\ncharacteristic of high temperature superconductors. Our results are compared to the\nstep-resistance models for the sake of discussion and clarity of the conclusions. Both\nSFCL models were integrated into a power system model built based on the UK power\nstandard, to study the impact of these protection strategies on the performance of\nthe overall electricity network. As a representative renewable energy source, a 90 MVA\nwind farm was considered for the simulations. Three fault conditions were simulated,\nand the figures for the fault current reduction predicted by both fault current limiting\nmodels have been compared in terms of multiple current measuring points and\nallocation strategies. Consequently, we have shown that the incorporation of the Eââ?¬â??J\ncharacteristics and thermal properties of the superconductor at the simulation level\nof electric power systems, is crucial for estimations of reliability and determining the\noptimal locations of resistive type SFCLs in distributed power networks. Our results\nmay help decision making by distribution network operators regarding investment and\npromotion of SFCL technologies, as it is possible to determine the maximum number\nof SFCLs necessary to protect against different fault conditions at multiple locations....
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